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? 2000 microchip technology inc. preliminary ds40197b-page 1 pic16hv540 high-performance risc cpu: ? only 33 single word instructions to learn all instructions are single cycle (200 ns) except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 12-bit wide instructions 8-bit wide data path seven special function hardware registers four-level deep hardware stack direct, indirect and relative addressing modes for data and instructions peripheral features: 8-bit real time clock/counter (tmr0) with 8-bit pro- grammable prescaler power-on reset (por) brown-out protection device reset timer (drt) with short rc oscilla- tor start-up time programmable watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation sleep timer 8 high voltage i/o 4 regulated i/o wake up from sleep on-pin change programmable code protection power saving sleep mode selectable oscillator options: - rc: low-cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal glitch filtering on mclr and pin change inputs pin configurations cmos technology: selectable on-chip 3v/5v regulator low-power, high-speed cmos eprom technol- ogy fully static design wide-operating voltage range: - 3.5v to 15v temperature range: - commercial: 0 c to 70 c - industrial: -40 c to 85 c low-power consumption - < 2 ma typical @ 5v, 4 mhz -15 a typical @ 3v, 32 khz -< 4.5 a typical standby current @ 15v (with wdt disabled), 0 c to 70 c pdip, soic, windowed cerdip ra1 ra0 osc1/clkin osc2/clkout v dd v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ssop pic16hv540 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 pic16hv540 10 enhanced pic16c54 eprom-based 8-bit cmos microcontroller with on-chip voltage regulator
pic16hv540 ds40197b-page 2 preliminary ? 2000 microchip technology inc. table of contents 1.0 general description ......................................................................................................... ............................ 3 2.0 pic16hv540 device varieties ................................................................................................. .................... 5 3.0 architectural overview ...................................................................................................... ........................... 7 4.0 memory organization ......................................................................................................... ....................... 11 5.0 i/o ports................................................................................................................... .................................. 19 6.0 timer0 module and tmr0 register............................................................................................. .............. 25 7.0 special features of the cpu ................................................................................................. .................... 31 8.0 instruction set summary ..................................................................................................... ...................... 43 9.0 development support ......................................................................................................... ....................... 55 10.0 electrical characteristics - pic16hv540 .................................................................................... ............... 61 11.0 dc and ac characteristics - pic16hv540..................................................................................... ........... 69 12.0 packaging information ...................................................................................................... ......................... 73 index .......................................................................................................................... .............................................. 79 on-line support ................................................................................................................ ....................................... 81 reader response ................................................................................................................ .................................... 82 pic16hv540 product identification system....................................................................................... ...................... 83 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please check our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: fill out and mail in the reader response form in the back of this data sheet. e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
? 2000 microchip technology inc. preliminary ds40197b-page 3 pic16hv540 1.0 general description the pic16hv540 from microchip technology is a low- cost, high-performance, 8-bit, fully-static, eprom- based cmos microcontroller. it is pin and software compatible with the pic16c5x family of devices. it employs a risc architecture with only 33 single word/ single cycle instructions. all instructions are single cycle except for program branches, which take two cycles. the pic16hv540 delivers performance an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly orthogonal resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy- to-use and easy-to-remember instruction set reduces development time significantly. the pic16hv540 is the first one-time-programmable (otp) microcontroller with an on-chip 3 volt and 5 volt regulator. this eliminates the need for an external reg- ulator in many applications powered from 9 volt or 12 volt batteries or unregulated 6 volt, 9 volt or 12 volt mains adapters. the pic16hv540 is ideally suited for applications that require very low standby current at high voltages. these typically require expensive low current regulators. the pic16hv540 is equipped with special features that reduce system cost and power requirements. the power- on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscilla- tor configurations to choose from, including the power- saving lp (low power) oscillator, cost saving rc oscilla- tor, and xt and hs for crystal oscillators. power saving sleep mode, watchdog timer and code protection fea- tures improve system cost, power and reliability. the uv erasable cerdip packaged versions are ideal for code development, while the cost-effective otp ver- sions are suitable for production in any volume. the customer can take full advantage of microchip ? s price leadership in otp microcontrollers, while benefiting from the otp ? s flexibility. the pic16hv540 is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer, and a full fea- tured programmer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic16hv540 fits in low-power battery applications such as co and smoke detection, toys, games, secu- rity systems and automobile modules. the eprom technology makes customizing of application programs (transmitter codes, receiver frequencies, etc.) extremely fast and convenient. the small footprint package, for through hole or surface mounting, make this microcontroller suitable for applications with space limitations. low-cost, low-power, high-performance, ease of use and i/o flexibility make the pic16hv540 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ? glue ? logic in larger systems, copro- cessor applications). 1.2 enhanced features 1.2.1 regulated i/o porta independent of core regulator porta i/o pads and osc2 output are powered by the regulated internal voltage v io . a maximum of 10ma per output is allowed, or a total of 40ma. the core itself is powered from the independently regulated supply v reg . 1.2.2 high voltage i/o portb all eight portb i/os are high voltage i/o. the inputs will tolerate input voltages as high as the v dd and out- puts will swing from v ss to the v dd . the input threshold voltages vary with supply voltage. (see electrical characteristics.) 1.2.3 wake-up on pin change on portb [0:3] four of the portb inputs latch the status of the pin at the onset of sleep mode. a level change on the inputs resets the device, implementing wake up on pin change (via warm reset). the pcwuf bit in the status register is reset to indicate that a pin change caused the reset condition. any pin change (glitch insensitive) of the opposite level of the initial value wakes up the device. this option can be enabled/disabled in option2 reg- ister. (see option2 register, register 4-3.) 1.2.4 wake-up on pin change with a slowly-rising voltage on portb [7] portb [7] also implements wake up from sleep, how- ever this input is specifically adapted so that a slowly rising voltage does not cause excessive power con- sumption. this input can be used with external rc cir- cuits for long sleep periods without using the internal timer and prescaler. this option is also enabled/dis- abled in option2 register. (the enable/disable bit is shared with the other 4 wake-up inputs.) the pcwuf bit in the status register is also shared with the other four wake-up inputs. 1.2.5 low-voltage (brown-out) detection a low voltage (brown-out) detect circuit optionally resets the device at a voltage level higher than that at which the picmicro ? device stops operating. the nom- inal trip voltages are 3.1 volts (for 5 volt operation) and 2.2 volt (for 3 volt operation), respectively. the core remains in the reset state as long as this condition holds (as if a mclr external reset was given). the brown-out trip level is user selectable, with built-in inter- locks. the brown-out detector is disabled at power-up and is activated by clearing the appropriate bit (boden ) in option2 register.
pic16hv540 ds40197b-page 4 preliminary ? 2000 microchip technology inc. 1.2.6 increased stack depth the stack depth is 4 levels to allow modular program implementation by using functions and subroutines. 1.2.7 enhanced watchdog timer (wdt) operation the wdt is enabled by setting fuse 2 in the configuration word. the wdt setting is latched and the fuse disabled during sleep mode to reduce current consumption. if the wdt is disabled by fuse 2, it can be enabled/dis- abled under program control using bit 4 in option2 reg- ister (swdten ). the software wdt control is disabled at power-up. the current consumption of the on-chip oscillator (used for the watchdog, oscillator startup timer and sleep timer) is less than 1 a (typical) at 3 volt operation. 1.2.8 reduced external rc oscillator startup time if the rc oscillator option is selected in the configura- tion word (fosc1=1 and fosco=1), the oscillator startup time is 1.0 ms nominal instead of 18 ms nomi- nal. this is applicable after power-up (por), either wdt interrupt or wake-up, external reset on mclr , pcwu (wake on pin change) and brown-out. 1.2.9 low-voltage operation of the entire cpu during sleep the voltage regulator can automatically lower the volt- age to the core from 5 volt to 3 volt during sleep, result- ing in reduced current consumption. this is an option bit (sl) in the option2 register. 1.2.10 glitch filters on wake-up pins and mclr glitch sensitive inputs for wake-up on pin change are filtered to reduce susceptibility to interference. a similar filter reduces false reset on mclr. 1.2.11 programmable clock generator when used in rc mode, the clkout pin can be used as a programmable clock output. the output is con- nected to tmr0, bit 0 and by setting the prescaler, clock out frequencies of clkin/8 to clkin/1024 can be generated. the clkout pin can also be used as a general purpose output by modifying tmr0, bit 0. table 1-1: pic16hv540 device pic16hv540 clock maximum frequency (mhz) 20 memory eprom program memory 512 ram data memory (bytes) 25 peripherals timer module(s) tmr0 packages i/o pins 12 voltage range (volts) 3.5v-15v number of instructions 33 packages 18-pin dip soic 20-pin ssop all picmicro ? devices have power-on reset, selectable wdt, selectable code protect and high i/o current capability.
? 2000 microchip technology inc. preliminary ds40197b-page 5 pic16hv540 2.0 pic16hv540 device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16hv540 product identification system at the back of this data sheet to specify the correct part number. for the pic16hv540 family of devices, there is one device type, as indicated in the device number: 1. hv , as in pic16hv540. these devices have eprom program memory and operate over the standard voltage range of 3.5 to 15 volts. 2.1 uv erasable devices the uv erasable versions, offered in cerdip pack- ages, are optimal for prototype development and pilot programs. uv erasable devices can be programmed for any of the four oscillator configurations. microchip ? s picstart ? and pro mate ? programmers both support program- ming of the pic16hv540. third party programmers also are available; refer to literature number ds00104 for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must be pro- grammed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and configuration bit options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. (please contact your microchip technology sales office for more details.) 2.4 serialized quick-turnaround- production (sqtp) devices microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequen- tial. serial programming allows each device to have a unique number which can serve as an entry code, password or id number. (please contact your microchip technology sales office for more details.)
pic16hv540 ds40197b-page 6 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 7 pic16hv540 3.0 architectural overview the high performance of the pic16hv540 can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16hv540 uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12- bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions. consequently, all instructions (33) execute in a single cycle (200ns @ 20mhz) except for program branches. the pic16hv540 address 512 x 12 of program mem- ory. all program memory is internal. the pic16hv540 can directly or indirectly address its register files and data memory. all special function reg- isters including the program counter are mapped in the data memory. the pic16hv540 has a highly orthogo- nal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ? special optimal situations ? make programming with the pic16hv540 simple yet efficient. in addition, the learn- ing curve is reduced significantly. the pic16hv540 device contains an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is either a file register or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1.
pic16hv540 ds40197b-page 8 preliminary ? 2000 microchip technology inc. figure 3-1: pic16hv540 block diagram v reg 3v/5v regulator v dd bod pc (pin change) filter rb7 pcwu 4 rb<3:0> rl/sl bodl/boden swdten (option2 register) osc1 osc2 mclr configuration word eprom 512 x 12 instruction register instruction decoder pc 9-11 9-11 12 12 9 8 direct address wdt time out stack 1 stack 2 stack 3 stack 4 high voltage translation rl/sl t0cki pin ? disable ? ? osc select ? 2 watchdog timer ? code protect ? 8 oscillator/ timing & control ? sleep ? clkout wdt/tmr0 prescaler 6 6 ? option ? from w from w general purpose register file (sram) 25 bytes ? tris 7 ? direct ram address 5 option2 option reg 5-7 8 fsr tmr0 data bus 8 8 8 8 8 4 4 4 from w from w ? tris 6 ? portb porta trisb trisa rb<7:0> ra<3:0> v io 3v/5v regulator ? tris 5 ? alu status w literals
? 2000 microchip technology inc. preliminary ds40197b-page 9 pic16hv540 table 3-1: pinout description - pic16hv540 name dip, soic no. ssop no. i/o/p type input levels description ra0 ra1 ra2 ra3 17 18 1 2 19 20 1 2 i/o i/o i/o i/o ttl ttl ttl ttl independently regulated bi-directional i/o port ? v io rb0 rb1 rb2 rb3 6 7 8 9 7 8 9 10 i/o i/o i/o i/o ttl ttl ttl ttl high-voltage bi-directional i/o port. sourced from v dd . wake-up on pin change rb4 rb5 rb6 10 11 12 11 12 13 i/o i/o i/o ttl ttl ttl rb7 13 14 i/o ttl wake-up on slow rising pin change. t0cki 3 3 i st clock input to timer 0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr/ v pp 4 4 i st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. voltage on the mclr / v pp pin must not exceed v dd (1) to avoid unintended entering of programming mode. osc1/clkin 16 18 i st oscillator crystal input/external clock source input. osc2/clkout 15 17 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2/clkout output is connected to tmr0, bit 0. frequencies of clkin/8 to clkin/1024 can be generated on this pin. v dd 14 15,16 p ? positive supply. v ss 55,6p ? ground reference. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input. note 1: v dd during programming mode can not exceed parameter pd1 called out in the pic16c5x programming specification (literature number ds30190).
pic16hv540 ds40197b-page 10 preliminary ? 2000 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the pro- gram counter is incremented every q1, and the instruc- tion is fetched from program memory and latched into instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock note 1: frequencies of clkin8 to clkin/1024 are possible. clkin/8 (1) all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ? flushed ? from the pipeline while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
? 2000 microchip technology inc. preliminary ds40197b-page 11 pic16hv540 4.0 memory organization pic16hv540 memory is organized into program mem- ory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one or two status register bits. for devices with a data memory register file of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file selection register (fsr). 4.1 program memory organization the pic16hv540 has a 9-bit program counter (pc) capable of addressing a 512 x 12 program memory space (figure 4-1). accessing a location above the physically implemented address will cause a wrap- around. the reset vector for the pic16hv540 is at 1ffh. a nop at the reset vector location will cause a restart at location 000h. figure 4-1: pic16hv540 program memory map and stack 4.2 data memory organization data memory is composed of registers, or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 regis- ter, the program counter (pc), the status register, the i/o registers (ports), and the file select register (fsr). in addition, special purpose registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic16hv540, the register file is composed of 10 special function registers and 25 general purpose registers (figure 4-2). 4.2.1 general purpose register file the register file is accessed either directly or indirectly through the file select register fsr (section 4.8). figure 4-2: pic16hv540 register file map 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions to control the opera- tion of the device (table 4-1). the special registers can be classified into two sets. the special function registers associated with the ? core ? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. pc<8:0> stack level 1 stack level 2 user memory space call, retlw 9 000h 1ffh reset vector 0ffh 100h on-chip program memory stack level 3 stack level 4 file address 00h 01h 02h 03h 04h 05h 06h 1fh indf (1) tmr0 pcl status fsr porta portb general purpose registers note 1: not a physical register. 0fh 10h 07h 08h
pic16hv540 ds40197b-page 12 preliminary ? 2000 microchip technology inc. table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset value on wake-up on pin change value on brown-out reset n/a tris i/o control registers (trisa, trisb) 1111 1111 1111 1111 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler --11 1111 --11 1111 --11 1111 --11 1111 n/a option2 contains control bits to configure pin changes, software enabled wdt, regulation and brown-out --11 1111 --uu uuuu --uu uuuu --xx xxxx 00h indf uses contents of fsr to address data memory (not a physical regis- ter) xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 1111 1111 1111 1111 03h status pcwuf pa 1 pa 0 to pd zdcc 1001 1xxx 100q quuu 000u uuuu x00x xxxx 04h fsr indirect data memory address pointer 111x xxxx 111u uuuu 111u uuuu 111x xxxx 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu ---- uuuu ---- xxxx 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx legend: shaded boxes = unimplemented or unused, ? = unimplemented, read as ? 0 ? (if applicable) x = unknown, u = unchanged, q = value depends on condition. note 1: the upper byte of the program counter is not directly accessible. see section 4.6 of the pic16hv540 data sheet (ds40197b) for an expla- nation of how to access these bits.
? 2000 microchip technology inc. preliminary ds40197b-page 13 pic16hv540 4.3 status register this register contains the arithmetic status of the alu, the reset status, and the page preselect bits for pro- gram memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable while the pcwuf bit is a read/write bit. there- fore, the result of an instruction with the status regis- ter as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status regis- ter because these instructions do not affect the z, dc or c bits from the status register. for other instruc- tions, which do affect status bits, see section 8.0, instruction set summary. register 4-1: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x pcwuf pa 1 pa 0 to pd z dc c r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: pcwuf : pin change reset bit 1 = after power-up reset (por) or sleep command 0 = after a wake-up on pin change event bit 6-5: not applicable bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
pic16hv540 ds40197b-page 14 preliminary ? 2000 microchip technology inc. 4.4 option register the option register is a 6-bit wide, write-only register which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option regis- ter. a reset sets the option<5:0> bits. example 4-1 illustrates how to initialize the option register. example 4-1: instructions for initializing option register movlw ? 0000 0111 ? b ; load option setup value into w option ; initialize option register register 4-2: option register u-0 u-0 w-1 w-1 w-1 w-1 w-1 w-1 ? ? t0cs t0se psa ps2 ps1 ps0 w = writable bit u = unimplemented bit - n = value at por reset bit7 0 bit 7-6: unimplemented bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps<2:0> : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 2000 microchip technology inc. preliminary ds40197b-page 15 pic16hv540 4.5 option2 register the option2 register is a 6-bit wide, write-only regis- ter which contains various control bits to configure the added features on the pic16hv540. a power-on reset sets the option2<5:0> bits. example 4-2 illustrates how to initialize the option2 register. example 4-2: instructions for initializing option2 register movlw ? 0001 0111 ? b ; load option2 setup value into w tris 0x07 ; initialize option2 register register 4-3: option2 register (tris 07h) note: all power-on resets will disable the brown-out detect circuit. all subsequent resets will not disable the brown-out detect if enabled. u-0 u-0 w-1 w-1 w-1 w-1 w-1 w-1 ? ? pcwu swdten rl sl bodl boden w = writable bit u = unimplemented bit - n = value at por reset bit7 0 bit 7-6: unimplemented bit 5: pcwu : wake-up on pin change 1 = disabled 0 = enabled bit 4: swdten : software controlled wdt enable bit 1 = wdt is turned off it the wdten configuration bit = 0 0 = wdt is on if the wdten configuration bit = 0; if wdten bit = 1, then swdten is ? don ? t care ? bit 3: rl : regulated voltage level select bit 1 = 5 volt 0 = 3 volt bit 2: sl: sleep voltage level select bit 1 = rl bit setting 0 = 3 volt bit 1: bodl : brown-out voltage level select bit 1 = rl bit setting, but sl during sleep 0 = 3 volt bit 0: boden : brown-out enabled 1 = disabled 0 = enabled
pic16hv540 ds40197b-page 16 preliminary ? 2000 microchip technology inc. 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next pro- gram instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. (figure 4-3). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are pro- vided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-3). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc , and bsf pc, 5 .. figure 4-3: loading of pc branch instructions - pic16hv540 4.6.1 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page i.e., the reset vector. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre- selected. therefore, upon a reset, a goto instruction at the reset vector location will automatically cause the pro- gram to jump to page 0. 4.7 stack pic16hv540 device has a 12-bit wide l.i.f.o. (last in, first out) hardware 4 level stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than four sequential call ? s are executed, only the most recent four return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than four sequential retlw ? s are executed, the stack will be filled with the address previously stored in level 4. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. upon any reset, the contents of the stack remain unchanged, however the program counter (pcl) will also be reset to 0. note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). pc 87 0 pcl 87 0 pcl reset to ? 0 ? instruction word instruction word goto instruction call or modify pcl instruction 9 10 x 11 x x x - not used x - not used pc 9 10 x 11 x x note 1: there are no status bits to indicate stack overflows or stack underflow condi- tions. note 2: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions.
? 2000 microchip technology inc. preliminary ds40197b-page 17 pic16hv540 4.8 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-3: indirect addressing register file 05 contains the value 10h register file 06 contains the value 0ah load the value 05 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 06) a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-4. example 4-4: how to clear ram using indirect addressing movlw 0x10 ;in itialize pointer movwf fsr ; to ram next clrf indf ;cl ear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is a 5-bit (pic16hv540) wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic16hv540: do not use banking. fsr<6:5> are unimplemented and read as '1's. figure 4-4: direct/indirect addressing note 1: bits 5 and 6 are unimplemented and read as 1 ? s. 2: for register map detail, see section 4.2. location select location select (note 1) indirect addressing direct addressing data memory (2) 0fh 10h bank 0 0 4 5 6 (fsr) 00h 1fh (opcode) 0 4 5 6 (fsr) (note 1)
pic16hv540 ds40197b-page 18 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 19 pic16hv540 5.0 i/o ports as with any other register, the i/o registers can be writ- ten and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin ? s input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance) since the i/o control registers (trisa, trisb) are all set. 5.1 porta porta is a 4-bit i/o register. only the low order 4 bits are used (ra3:ra0). bits 7-4 are unimplemented and read as '0's. the inputs will tolerate input voltages as high as v io and outputs will swing from v ss to v io . the internal voltage regulator v io powers porta i/o pads. the internal regulator output, v io , is switchable between 3vdc and 5vdc, via the (rl) bit in the option2 register. 5.2 portb portb is an 8-bit i/o register (portb<7:0>). all 8 portb i/os are high voltage i/o. the inputs will toler- ate input voltages as high as v dd and outputs will swing from v ss to v dd . in addition, 5 of the portb pins can be configured for the wake-up on change feature. pins rb0, rb1, rb2 and rb3 latch the state of the pin at the onset of sleep mode. (no ? dummy ? read of the portb pins is required prior to executing the sleep instruc- tion.) a level change on the input resets the device, implementing wake-up on pin change. the pcwuf bit in the status register is cleared to indicate that a pin change caused the reset. this feature can be enabled/ disabled in the option2 register. portb pin rb7 also exhibits this wake-up on pin high feature but is specially adapted for a slow-rising input signal. this special feature prevents excessive power consumption when desiring long sleep periods without using the watchdog timer and prescaler. pcwuf bit in the status register is cleared to indicate that a pin change caused the reset. this feature can be enabled/ disabled in the option2 register. only pins configured as inputs can cause this wake-up on pin change to occur. to prevent false wake-up on pin change events on pins rb<0:3>, the pin state must be driven to a logic 1 or logic 0 and not left floating during the ? sleep ? state. for pin rb7, the pin state must be driven to logic 0 and allowed to ramp to a logic 1 for correct operation. 5.3 tris registers the output driver control registers are loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corre- sponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the tris registers are ? write-only ? and are set (output drivers disabled) upon reset. 5.4 i/o interfacing the equivalent circuit for the porta and portb i/o pins are shown in figure 5-1 through figure 5-4. all ports may be used for both input and output operation. for input operations, these ports are non-latching. any input must be present until read by an input instruction (e.g., movf portb, w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit (in trisa, trisb) must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin can be programmed individually as input or output. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
pic16hv540 ds40197b-page 20 preliminary ? 2000 microchip technology inc. figure 5-1: block diagram of porta<0:3> pins figure 5-2: block diagram of portb<0:3> pins data bus q d q ck q d q ck p n wr porta data tris rd porta v ss v io ra0-ra3 pins w reg latch latch reset tris porta v io v ss data bus q d q ck q d q ck p n wr portb data tris rd portb v ss v dd rb0-rb3 pins w reg latch latch tris portb v dd step-up circuit v dd d q ck q step-down circuit rd portb ? sleep ? m u x wake-up on pin change v ss
? 2000 microchip technology inc. preliminary ds40197b-page 21 pic16hv540 figure 5-3: block diagram of portb<4:6> pins figure 5-4: block diagram of portb<7> pin data bus q d q ck q d q ck p n wr portb data tris rd portb v ss v dd rb4-rb6 pins w reg latch latch tris portb v dd step-up circuit v dd step-down circuit v ss data bus q d q ck q d q ck p n wr portb data tris rd portb v ss v dd rb7 pin w reg latch latch tris portb v dd step-up circuit v dd step-down circuit wake-up on pin change v ss p v dd
pic16hv540 ds40197b-page 22 preliminary ? 2000 microchip technology inc. table 5-1: summary of port registers 5.5 i/o programming considerations 5.5.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu, bit5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bi-direc- tional i/o pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/ o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ( ? wired-or ? , ? wired-and ? ). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial port settings ; portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ;01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp movlw 03fh ; tris portb ;10pp pppp 10pp pppp ; ;note that the user may have expected the pin ;values to be 00pp pppp. the 2nd bcf caused ;rb7 to be latched as the pin value (high). 5.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-5). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset value on wake-up on pin change value on brown-out reset n/a tris i/o control registers (trisa, trisb) 1111 1111 1111 1111 1111 1111 1111 1111 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu ---- uuuu ---- xxxx 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 03h status pcwuf pa 1 pa 0 to pd z dc c 100x xxxx 100q quuu 000u uuuu x00x xxxx n/a option2 ? ? pcwu swdten rl sl bodl boden --11 1111 --uu uuuu --uu uuuu --xx xxxx legend: shaded boxes = unimplemented, read as ? 0 ? , ? = unimplemented, read as '0', x = unknown, u = unchanged.
? 2000 microchip technology inc. preliminary ds40197b-page 23 pic16hv540 figure 5-5: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb nop port pin sampled here nop movf portb,w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. (read portb) port pin written here
pic16hv540 ds40197b-page 24 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 25 pic16hv540 6.0 timer0 module and tmr0 register the timer0 module has the following features: 8-bit timer/counter register, tmr0 - readable and writable 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module, while figure 6-2 shows the electrical structure of the timer0 input. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-3 and figure 6-4). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the incrementing edge is determined by the source edge select bit t0se (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler may be used by either the timer0 mod- ule or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are select- able. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-6). 3: bit 0 of tmr0 will be output on osc2/clkout pin when rc oscillator mode is selected. t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync ? sleep ? internal oscillator drive circuit 7 0 m u x oscillator mode select (3) osc2/ clkout
pic16hv540 ds40197b-page 26 preliminary ? 2000 microchip technology inc. figure 6-2: electrical structure of t0cki pin figure 6-3: timer0 timing: internal clock/no prescale figure 6-4: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset value on wake-up on pin change value on brown-out reset 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx n/a option ? ? t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 --11 1111 --11 1111 legend: shaded cells: unimplemented bits, - = unimplemented, x = unknown, u = unchanged. v ss v ss r in schmitt trigger n input buffer t0cki pin note 1: esd protection circuits. (1) (1) pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t 0
? 2000 microchip technology inc. preliminary ds40197b-page 27 pic16hv540 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2: 3: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic16hv540 ds40197b-page 28 preliminary ? 2000 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt) (wdt postscaler not implemented on pic16c52), respectively (section 6.1.2). for simplicity, this counter is being referred to as ? prescaler ? through- out this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is nei- ther readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ? on the fly ? during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) 1. clrwdt ;clear wdt 2. clrf tmr0 ;clear tmr0 & prescaler 3. movlw '00xx1111 ? b ;these 3 lines (5, 6, 7) 4. option ; are required only if ; desired 5. clrwdt ;ps<2:0> are 000 or 001 6. movlw '00xx1xxx ? b ;set postscaler to 7. option ; desired wdt rate to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switch- ing the prescaler. example 6-2: changing prescaler (wdt timer0) clrwdt ;clear wdt and ;prescaler movlw ? xxxx0xxx ? ;select tmr0, new ;prescale value and ;clock source option 6.3 programmable clock generator when the pic16hv540 is programmed to operate in the rc oscillator mode, the clkout pin is connected to the compliment state of tmr0<0>. use of the pres- caler rate select bits psa:ps0 in the option register will provide for frequencies of clkin/8 to clkin/1024 on the clkout pin. example 6-3: in addition to this mode of operation, tmr0<0> can be toggled via the bcf and bsf bit type instructions. for this mode, the t0cs bit in the option register must be set to 1. this setting configures tmr0 to increment on the t0cki pin. to set the clkout pin high, a bcf tmr0,0 instruction is used and to set the clkout pin low, the bsf tmr0,0 instruction is used. the t0cki pin should be pulled high or low to prevent false state changes on the clkout pin. fosc prescaler setting/clkout frequency clkin/1024 clkin/8 1mhz 976 hz 125 khz 2mhz 1953 hz 250 khz 3mhz 2930 hz 375 khz 4mhz 3906 hz 500 khz
? 2000 microchip technology inc. preliminary ds40197b-page 29 pic16hv540 figure 6-6: block diagram of the timer0/wdt prescaler t0cki t0se (1) pin t cy ( = fosc/4) sync 2 cycles 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa (1) 0 1 0 1 wdt time-out ps<2:0> (1) 8 psa (1) wdten 0 1 0 1 data bus 8 psa (1) t0cs (1) m u x m u x u x tmr0 reg ? sleep ? internal oscillator drive circuit 7 0 m u x oscillator mode select osc2/ clkout configuration bit swdten bit (2) note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. 2: swdten is a bit in the option2 register.
pic16hv540 ds40197b-page 30 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 31 pic16hv540 7.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. the pic16hv540 family of micro- controllers has a host of such features intended to max- imize system reliability, minimize cost through elimination of external components, provide power sav- ing operating modes and offer code protection. these features are: oscillator selection reset power-on reset (por) brown-out detect device reset timer (drt) wake-up from sleep on pin change enhanced watchdog timer (wdt) sleep code protection the pic16hv540 family has a watchdog timer which can be shut off only through configuration bit wdten. it runs off of its own rc oscillator for added reliability. there is an 18 ms delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low cur- rent power-down mode. the user can wake up from sleep through external reset or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 7.1 configuration bits configuration bits can be programmed to select various device configurations. two bits are for the selection of the oscillator type and one bit is the watchdog timer enable bit. nine bits are code protection bits (figure 7- 1) for the pic16hv540 devices. register 7-1: configuration word for pic16hv540 cp cp cp cp cp cp cp cp cp wdten f osc 1f osc 0 register:config address (1) :0fffh bit11 bit0 bit 11-3: cp: code protection bits 1 = code protection off 0 = code protection on bit 2: wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) bit 1-0: f osc <1:0>: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic16c5x programming specification (literature number ds30190) to determine how to access the configuration word.
pic16hv540 ds40197b-page 32 preliminary ? 2000 microchip technology inc. 7.2 oscillator configurations 7.2.1 oscillator types the pic16hv540 can be operated in four different oscillator modes. the user can program two configura- tion bits (fosc1:fosc0) to select one of these four modes: lp: low power crystal xt: crystal/resonator hs: high speed crystal/resonator rc: resistor/capacitor 7.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 7-1). the pic16hv540 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, lp or hs modes, the device can have an external clock source drive the osc1/clkin pin (figure 7-2). figure 7-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 7-2: external clock input operation (hs, xt or lp osc configuration) table 7-1: capacitor selection for ceramic resonators - pic16hv540 table 7-2: capacitor selection for crystal oscillator - pic16hv540 note: not all oscillator selections available for all parts. see section 7.1. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen (approx. value = 10 m ? ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16hv540 osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-33 pf 10-22 pf 68-100 pf 15-33 pf 10-22 pf hs 8.0 mhz 16.0 mhz 10-22 pf 10 pf 10-22 pf 10 pf note: these values are for design guidance only. since each resonator has its own charac- teristics, the user should consult the reso- nator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15 pf 15 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15 pf 15 pf hs 4 mhz 8 mhz 20 mhz 15 pf 15 pf 15 pf 15 pf 15 pf 15 pf note 1: for v dd > 4.5v, c1 = c2 30 pf is recommended. 2: these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. note: if you change from this device to another device, please verify oscillator characteris- tics in your application. clock from ext. system osc1 osc2 pic16hv540 open
? 2000 microchip technology inc. preliminary ds40197b-page 33 pic16hv540 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crys- tal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well- designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 7-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiome- ters bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-3: external parallel resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) figure 7-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator cir- cuit. the 330 ? resistors provide the negative feedback to bias the inverters in their linear region. figure 7-4: external series resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) 7.2.4 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (rext) and capacitor (cext) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 7-5 shows how the r/c combination is con- nected to the pic16hv540. for rext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m ? ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. note: if you change from this device to another device, please verify oscillator characteris- tics in your application. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16hv540 clkin to other devices osc2 100k note: if you change from this device to another device, please verify oscillator characteris- tics in your application. 330 74as04 74as04 pic16hv540 clkin to other devices xtal 330 74as04 0.1 f osc2 100k
pic16hv540 ds40197b-page 34 preliminary ? 2000 microchip technology inc. the electrical specifications sections show rc fre- quency variation from part to part due to normal pro- cess variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications sections for vari- ation of oscillator frequency due to v dd for given rext/ cext values as well as frequency variation due to oper- ating temperature for given r, c, and v dd values. when used in rc mode, the clkout pin can be used as a programmable clock output. the output is connected to tmr0, bit 0, and by setting the prescaler rate select bits, clock out frequencies of clkin/8 to clkin/1024 can be generated. figure 7-5: rc oscillator mode 7.3 reset pic16hv540 devices may be reset in one of the follow- ing ways: power-on reset (por) mclr reset (normal operation) mclr wake-up reset (from sleep) wdt reset (normal operation) wdt wake-up reset (from sleep) wake-up from sleep on pin change brown-out detect table 7-3 shows these reset conditions for the pcl and status registers. some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ? reset state ? on power-on reset (por), mclr or wdt reset. a mclr , wdt wake-up from sleep or wake- up from sleep on pin change also results in a device reset, and not a continuation of operation before sleep. the to and pd bits (status <4:3>) and pcwuf (status<7>) are set or cleared depending on the dif- ferent reset conditions (section 7.9). these bits may be used to determine the nature of the reset. table 7-4 lists a full description of reset states of all reg- isters. figure 7-6 shows a simplified block diagram of the on-chip reset circuit. note: if you change from this device to another device, please verify oscillator characteris- tics in your application. v dd r ext c ext v ss osc1 internal clock osc2/clkout tmr0, 0 pic16hv540 n
? 2000 microchip technology inc. preliminary ds40197b-page 35 pic16hv540 table 7-3: reset conditions for special registers table 7-4: reset conditions for all registers figure 7-6: simplified block diagram of on-chip reset circuit condition pcl addr: 02h status addr: 03h power-on reset 1111 1111 1001 1xxx mclr reset (normal operation) 1111 1111 u00u uuuu (1) mclr wake-up (from sleep) 1111 1111 1001 0uuu wdt reset (normal operation) 1111 1111 u000 1uuu (2) wdt wake-up (from sleep) 1111 1111 1000 0uuu wake-up from sleep on pin change 1111 1111 000u uuuu brown-out reset 1111 1111 x00x xxxx legend: u = unchanged, x = unknown, - = unimplemented read as ? 0 ? . note 1: to and pd bits retain their last value until one of the other reset conditions occur. 2: the clrwdt instruction will set the to and pd bits. register address power-on reset mclr or wdt reset wake-up on pin change brown-out reset wn/a xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx tris n/a 1111 1111 1111 1111 1111 1111 1111 1111 option n/a --11 1111 --11 1111 --11 1111 --11 1111 option2 n/a --11 1111 --uu uuuu --uu uuuu --xx xxxx indf 00h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx pcl (1) 02h 1111 1111 1111 1111 1111 1111 1111 1111 status (1) 03h 1001 1xxx 100? ?uuu 000u uuuu x00x xxxx fsr 04h 111x xxxx 111u uuuu 111u uuuu 111x xxxx porta 05h ---- xxxx ---- uuuu ---- uuuu ---- xxxx portb 06h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx general purpose register files 07-1fh xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx legend: u = unchanged, x = unknown, - = unimplemented, read as ? 0 ? , q = see tables in section 7.10 for possible values. ? = value depends on condition. note 1: see table 7-3 for reset value for specific conditions. 8-bit asynch ripple counter (start-up timer) sq r q v dd mclr /v pp pin power-up detect on-chip rc osc por (power-on reset) wdt time-out reset chip reset wdt bor (brown-out reset)
pic16hv540 ds40197b-page 36 preliminary ? 2000 microchip technology inc. 7.4 power-on reset (por) the pic16hv540 incorporates on-chip power-on reset (por) circuitry which provides an internal chip reset for most power-up situations. to use this feature, the user merely ties the mclr /v pp pin to v dd . a sim- plified block diagram of the on-chip power-on reset cir- cuit is shown in figure 7-7. the power-on reset circuit and the device reset timer (section 7.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. a power-up example where mclr is not tied to v dd is shown in figure 7-8. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-9, the on-chip power-on reset feature is being used (mclr and v dd are tied together). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 7-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses a high on the mclr / v pp pin , and when the mclr / v pp pin (and v dd ) actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function cor- rectly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 7-7). for more information on pic16hv540 por, see power-up considerations - an522 in the embedded control handbook . the por circuit does not produce an internal reset when v dd declines. figure 7-7: external power-on reset circuit (for slow v dd power-up) note: when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, tempera- ture, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. c r1 r d mclr pic16hv540 v dd v dd external power-on reset circuit is required only if v dd power-up is too slow. the diode d helps dis- charge the capacitor quickly when v dd powers down. r < 40 k ? is recommended to make sure that volt- age drop across r does not violate the device elec- trical specification. r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c in the event of mclr pin breakdown due to electrostatic dis- charge (esd) or electrical overstress (eos).
? 2000 microchip technology inc. preliminary ds40197b-page 37 pic16hv540 figure 7-8: time-out sequence on power-up (mclr not tied to v dd ) figure 7-9: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 7-10: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 v dd min.
pic16hv540 ds40197b-page 38 preliminary ? 2000 microchip technology inc. 7.5 device reset timer (drt) in the pic16hv540, the device reset timer (drt) runs any time the device is powered up. drt runs from reset and varies based on oscillator selection (see table 7-5). the drt provides a fixed 18 ms nominal time-out on reset. the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows vdd to rise above vdd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after the voltage on the mclr /v pp pin has reach a logic high (v ih ) level. thus, external rc networks connected to the mclr input are not required in most cases, allow- ing for savings in cost-sensitive and/or space restricted applications. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out, mclr reset, wake-up from sleep on pin change and brown-out reset. when the external rc oscillator mode is selected, all drt periods, after the initial por, are 1 ms (typical). table 7-5: drt (device reset timer period) 7.6 brown-out detect (bod) the pic16hv540 has on-chip brown-out detect cir- cuitry. if enabled and if the internal power, v reg, falls below parameter b vdd (see section 10.1 ), for greater time than parameter t bod (see table 10-3) the brown- out condition will reset the chip. a reset is not guaran- teed if v reg falls below b vdd for less time than param- eter (t bod ). on resets (brown-out, watchdog, mclr and wake-up on pin change), the chip will remain in reset until v reg rises above b vdd . once the b vdd threshold has been met the drt will now be invoked and will keep the chip in reset an additional 18ms (lp, xt and hs oscillator modes) or 1ms for extrc. if v reg drops below b vdd while the drt is running, the chip will go back into a brown-out reset and the drt will be re-initialized. once v reg rises above the b vdd , the drt will execute the specified time period. figure 7-11 shows typical brown-out situations. the brown-out detect circuit can be disabled or enabled by setting the boden bit in the option2 sfr. the brown-out detect is disabled upon all power- on resets (por). 7.6.1 implementing the on-chip bod circuit the pic16hv540 bod circuitry differs from ? conven- tional ? brown-out detect circuitry in that the bod cir- cuitry on the pic16hv540 does not directly detect ? dips ? in the external v dd supply voltage but rather the internal v reg . the functionality of the bod circuitry ensures that program execution will halt and a reset state will be entered into prior to the internal logic becoming corrupted. the bod circuit has two select- able voltage settings, nominally 5v and 3v. each regu- lation voltage setting with its associated minimum and maximum b vdd parameters has an intended opera- tional mode that must be carefully considered. for the 5v v reg setting, the minimum b vdd parameter is 2.7v . this minimum b vdd voltage is below the part v dd minimum requirements. this operational setting is primarily intended for use when the pic16hv540 is operating at 4mhz and v dd > 5.5v. for the 3v v reg setting, the minimum b vdd parameter is 1.8v. this minimum b vdd voltage is below the part v dd minimum requirements. this operational setting is primarily intended for use when the pic16hv540 is in sleep. ram retention is protected by the 1.8v trip level. for the regulation and brown-out circuits to function as intended the applied v dd is nominally 0.5v greater than the regulation voltage setting. finally, if the internal brown-out circuit is deemed not to meet system design requirements then an external brown-out protection circuit may be required. microchip offers a complete family of voltage supervisor products which can meet most design requirements. oscillator configuration por reset subsequent resets extrc 18 ms (typical) 1 ms (typical) lp, xt & hs 18 ms (typical) 18 ms (typical)
? 2000 microchip technology inc. preliminary ds40197b-page 39 pic16hv540 figure 7-11: brown-out situations 7.7 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external com- ponents. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins have been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watch- dog timer reset. the watchdog timer is enabled/disabled by a device configuration bit (see figure 7-1). if the wdt is enabled, software execution may not disable this func- tion. when the wdten configuration bit is cleared, the swdten bit, option2<4>, enables/disables the operation of the wdt. 7.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writ- ing to the option register. thus, time-out a period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several sec- onds before a wdt time-out occurs. 7.7.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the max- imum sleep time before a wdt wake-up reset. 7.8 internal voltage regulators the pic16hv540 has 2 internal voltage regulators. the porta i/o pads and osc2 are powered by one internal voltage regulator v io , while the second internal voltage regulator v reg , powers the picmicro ? device core. both regulated voltage levels can be synchro- nously switched in the active modes between 3v and 5v through bit ? rl ? in the option2 register. in addi- tion, the ? sl ? bit in the option2 register can be used to control the core ? s regulated voltage level during sleep mode. v reg regulates the 15v power applied to the v dd pin. the on-chip brown-out detect circuitry monitors the cpu regulated voltage v reg , for determining if a brown-out reset is generated (see section 7.6 for more details on the bod). the regulator circuits are identical in functional nature but only the v io regulator voltage can be measured, externally (see section 10.1 for v io parameters). the operational voltage range and pin loading requirements must be considered to ensure proper system operation. for example, if 3v regulation is implemented during the sleep mode and 40ma is being sourced from porta, the v io regulation voltage may approach the specified minimum voltage. this may be an issue to consider for connections to external circuitry. likewise, if zero cur- rent is sourced from the porta pins, the regulation 18 ms (2) bv dd (1) v reg internal reset v reg internal reset v reg internal reset 18 ms (2) 18 ms (2) 18 ms (2) bv dd (1) bv dd (1) note 1: bv dd depends on selection of bit ? rl ? in option2 sfr. 2: drt time depends on which oscillator mode is selected and which reset state the part is in.
pic16hv540 ds40197b-page 40 preliminary ? 2000 microchip technology inc. voltage may approach the maximum value. again this condition should be considered when interfacing to external circuitry. in addition, the voltage level applied to the external v dd pin and operational temperature affects the internal regulation voltage. figure 7-12: watchdog timer block diagram table 7-6: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset value on wake-up on pin change value on brown-out reset n/a option ? ? t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 --11 1111 --11 1111 n/a option2 ? ? pcwu swdten rl sl bodl boden --uu uuu --uu uuuu --uu uuuu --xx xxxx legend: shaded boxes = not used by watchdog timer, ? = unimplemented, read as '0', u = unchanged, x = unknown. postscaler watchdog timer wdten configuration bit swdten bit from tmr0 clock source m u x 0 1 psa postscaler 8 - to - 1 mux ps<2:0> to t m r 0 1 psa mux 0 wdt time-out note: t0cs, t0se, psa, ps<2:0> are bits in the option register.
? 2000 microchip technology inc. preliminary ds40197b-page 41 pic16hv540 7.9 time- ou t sequence and power -do wn s tatus bits ( to / pd / pcwuf ) the to , p d and pcwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr , watch- dog timer (wdt) reset, wdt wake-up reset, or wake-up from sleep on pin change. these status bits are only affected by events listed in ta bl e 7 - 8 . table 7-3 lists the reset conditions for the special func- tion registers, while table 7-4 lists the reset conditions for all the registers. 7.10 power- do wn mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.10.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared, the pcwuf bit (status<7>) is set and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driv- ing low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr /v pp pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the mclr / v pp pin must be at a logic high level (v ih mclr ). 7.10.2 wake-up from sleep the device can wake up from sleep through one of the following events: 1. an external reset input on mclr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pins portb:<0-3,7> when wake-up on pin change is enabled. 4. brown-out reset. these events cause a device reset. the to and pd and pcwuf bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time- out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the pcwuf bit indicates a change in state while in sleep at pins portb:<0-3,7> (since the sleep state was entered). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. table 7-7: to /pd /pcwuf status after reset pcwuf to pd reset was caused by 111 power-up (por) uuu mclr reset (normal operation) (1) u10 mclr wake-up reset (from sleep) u01 wdt reset (normal operation) u00 wdt wake-up reset (from sleep) 0uu wake-up from sleep on pin change xxx brown-out reset legend: u = unchanged, x = unknown note 1: the to and pd and pcwuf bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the to and pd and pcwuf status bits. table 7-8: events affecting to /pd status bits event pcwuf to pd remarks power-up 1 11 wdt time-out u 0 u no effect on pd sleep instruction 1 10 clrwdt instruction u 11 wake-up from sleep on pin change 0 uu legend: u = unchanged note: a wdt time-out will occur regardless of the status of the to bit. a sleep instruction will be executed, regardless of the status of the pd bit. table 7-7 reflects the status of to and pd after the corresponding event.
pic16hv540 ds40197b-page 42 preliminary ? 2000 microchip technology inc. 7.11 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 7.12 id locations four memory locations are designated as id locations where the user can store checksum or other code-iden- tification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as ? 1 ? s. note: microchip does not recommend code pro- tecting windowed devices. note: microchip will assign a unique pattern number for qtp and sqtp requests and for rom devices. this pattern number will be unique and traceable to the submitted code.
? 2000 microchip technology inc. preliminary ds40197b-page 43 pic16hv540 8.0 instruction set summary each pic16hv540 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the pic16hv540 instruc- tion set summary in table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. table 8-1 shows the opcode field descrip- tions. for byte-oriented instructions, ? f ? represents a file reg- ister designator and ? d ? represents a destination desig- nator. the file register designator is used to specify which one of the 32 file registers is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is ? 0 ? , the result is placed in the w register. if ? d ? is ? 1 ? , the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the number of the file in which the bit is located. for literal and control operations, ? k ? represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. figure 8-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ? h ? signifies a hexadecimal digit. figure 8-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don ? t care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for com- patibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ? f ? ) default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of i talics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic16hv540 ds40197b-page 44 preliminary ? 2000 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k k k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd ,pcwuf none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto . (see individual device data sheets, memory section/indirect data addressing, indf and fsr regis- ters) 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 5 or 6 causes the contents of the w register to be written to the tristate latches of porta or b respectively. a '1' forces the pin to a hi-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
? 2000 microchip technology inc. preliminary ds40197b-page 45 pic16hv540 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d [0,1] operation: (w) + (f) (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register ? f ? . if ? d ? is 0 the result is stored in the w register. if ? d ? is ? 1 ? the result is stored back in register ? f ? . words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are and ? ed with the eight-bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example: andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d [0,1] operation: (w) .and. (f) (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are and ? ed with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic16hv540 ds40197b-page 46 preliminary ? 2000 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none encoding: 0101 bbbf ffff description: bit ? b ? in register ? f ? is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit ? b ? in register ? f ? is 0 then the next instruction is skipped. if bit ? b ? is 0 then the next instruction fetched during the current instruction execution is discarded, and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code before instruction pc = address (here) after instruction if flag<1>=0, pc = address (true) ; if flag<1>=1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit ? b ? in register ? f ? is ? 1 ? then the next instruction is skipped. if bit ? b ? is ? 1 ? , then the next instruction fetched during the current instruction execution, is discarded and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true ? ? ? before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1>=1, pc = address (true)
? 2000 microchip technology inc. preliminary ds40197b-page 47 pic16hv540 call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top of stack; k pc<7:0>; (status<6:5>) pc<10:9>; 0 pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from sta- tus<6:5>, pc<8> is cleared. call is a two cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z encoding: 0000 011f ffff description: the contents of register ? f ? are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 to; 1 pd status affected: to , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 to =1 pd =1
pic16hv540 ds40197b-page 48 preliminary ? 2000 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z encoding: 0010 01df ffff description: the contents of register ? f ? are comple- mented. if ? d ? is 0 the result is stored in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 (dest) status affected: z encoding: 0000 11df ffff description: decrement register ? f ? . if ? d ? is 0 the result is stored in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register ? f ? are decre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . if the result is 0, the next instruction, which is already fetched, is discarded and an nop is executed instead mak- ing it a two cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status<6:5> pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there)
? 2000 microchip technology inc. preliminary ds40197b-page 49 pic16hv540 incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z encoding: 0010 10df ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . if the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an nop is executed instead making it a two cycle instruc- tion. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here +1) iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are or ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0
pic16hv540 ds40197b-page 50 preliminary ? 2000 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z encoding: 0010 00df ffff description: the contents of register ? f ? is moved to destination ? d ? . if ? d ? is 0, destination is the w register. if ? d ? is 1, the destination is file register ? f ? . ? d ? is 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal ? k ? is loaded into the w register. the don ? t cares will assem- ble as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to regis- ter 'f' . words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop
? 2000 microchip technology inc. preliminary ds40197b-page 51 pic16hv540 option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example optio n before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal ? k ? . the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ;w now has table ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register ? f ? are rotated one bit to the left through the carry flag. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register ? f ? c register ? f ?
pic16hv540 ds40197b-page 52 preliminary ? 2000 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 to ; 0 pd 1 pcwuf status affected: to , pd , pcwuf encoding: 0000 0000 0011 description: time-out status bit (to ) is set. the power down status bit (pd ) is cleared. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d [0,1] operation: (f) ? (w) ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2 ? s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive example 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero example 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative
? 2000 microchip technology inc. preliminary ds40197b-page 53 pic16hv540 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register ? f ? are exchanged. if ? d ? is 0 the result is placed in w register. if ? d ? is 1 the result is placed in register ? f ? . words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 5, 6 or 7 operation: (w) tris register f status affected: none encoding: 0000 0000 0fff description: tris register ? f ? (f = 5, 6, or 7*) is loaded with the contents of the w register words: 1 cycles: 1 example tris porta before instruction w=0xa5 after instruction trisa = 0xa5 *a tris 7 operation will update the option2 sfr. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xor ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic16hv540 ds40197b-page 54 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 55 pic16hv540 9.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian simulators - mplab-sim software simulator emulators - mplab-ice real-time in-circuit emulator - picmaster ? /picmaster-ce in-circuit emulator - icepic ? in-circuit debugger - mplab-icd for pic16f877 device programmers -pro mate ? ii universal programmer - picstart ? plus entry-level prototype programmer low-cost demonstration boards - simice - picdem-1 - picdem-2 - picdem-3 - picdem-17 - seeval ? -k ee l oq ? 9.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows ? -based applica- tion which contains: multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) a full featured editor a project manager customizable tool bar and key mapping a status bar on-line help mplab allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source files - absolute listing file - object code the ability to use mplab with microchip ? s simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 9.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcu ? s. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: mpasm and mplink are integrated into mplab projects. mpasm allows user defined macros to be created for streamlined assembly. mpasm allows conditional assembly for multi pur- pose source files. mpasm directives allow complete control over the assembly process. 9.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi ? c ? compilers and inte- grated development environments for microchip ? s pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16hv540 ds40197b-page 56 preliminary ? 2000 microchip technology inc. 9.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: mplink works with mpasm and mplab-c17 and mplab-c18. mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: mplib makes linking easier because single librar- ies can be included instead of many smaller files. mplib helps keep code maintainable by grouping related modules together. mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 9.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 9.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, ? make ? and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive development tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 9.7 picmaster/picmaster ce the picmaster system from microchip technology is a full-featured, professional quality emulator system. this flexible in-circuit emulator provides a high-quality, universal platform for emulating microchip 8-bit picmicro microcontrollers (mcus). picmaster sys- tems are sold worldwide, with a ce compliant model available for european union (eu) countries. 9.8 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchangeable personality modules or daughter boards. the emulator is capable of emulating without target application circuitry being present. 9.9 mplab-icd in-circuit debugger microchip ? s in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 2000 microchip technology inc. preliminary ds40197b-page 57 pic16hv540 9.10 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 9.11 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 9.12 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchip ? s simulator mplab-sim. both simice and mplab-sim run under microchip technology ? s mplab integrated development environment (ide) software. specifically, simice provides hardware sim- ulation for microchip ? s pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrollers. simice works in conjunction with mplab-sim to pro- vide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valu- able debugging tool for entry-level system develop- ment. 9.13 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchip ? s microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 9.14 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 9.15 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
pic16hv540 ds40197b-page 58 preliminary ? 2000 microchip technology inc. 9.16 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 9.17 seeval evaluation and programming system the seeval seeprom designer ? s kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 9.18 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 2000 microchip technology inc. preliminary ds40197b-page 59 pic16hv540 table 9-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ? -ice ** picmaster/picmaster-ce icepic ? low-cost in-circuit emulator debugger mplab ? -icd in-circuit debugger * * programmers picstart ? plus low-cost universal dev. kit ** pro mate ? ii universal programmer ** demo boards and eval kits simice picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid? programmer ? s kit 125 khz microid developer ? s kit 125 khz anticollision microid developer ? s kit 13.56 mhz anticollision microid developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? -icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16hv540 ds40197b-page 60 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 61 pic16hv540 10.0 electrical characteristics - pic16hv540 absolute maximum ratings ? ambient temperature under bias................................................................................................. ............. ? 20 c to +85 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on v dd with respect to v ss ...................................................................................................................0 to +16v voltage on mclr with respect to v ss ................................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ? 0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw max. current out of v ss pin ........................................................................................................................... ........150 ma max. current into v dd pin ........................................................................................................................... ...........100 ma max. current into an input pin (t0cki only) ..................................................................................................................... 500 a input clamp current, i ik (v i < 0 or v i > v dd ) ................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................10 ma max. output current sourced by a single i/o port a or b ........................................................................ .................40 ma max. output current sourced by a single i/o port a or b ....................................................................... .................50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ? low ? level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16hv540 ds40197b-page 62 preliminary ? 2000 microchip technology inc. 10.1 dc characteristics: pic16hv540-04, 20 (commercial) pic16hv540-04i, 20i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym. min. typ. (1) max. units conditions supply voltage v dd 3.5 4.5 ? 15 15 v v lp, xt and rc modes hs mode ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section on power-on reset for details. v dd rise rate to ensure power-on reset s vdd 0.05 v dd v/ms see section 7.4 for details on power-on reset supply current (3) hs option xt and rc (4) options lp option i dd ? ? ? 5 1.8 300 20 3.3 500 ma ma a f osc = 20 mhz, v dd = 15v, v reg = 5v f osc = 4 mhz, v dd = 15v, v reg = 5v f osc = 32 khz, v dd = 15v, v reg = 5v, wdt disabled power-down current (5)(6) i pd ? ? ? ? 4.5 0.25 1.8 1.4 20 14 10 5 a a a a v dd = 15v, v reg = 5v sleep timer enable, bod disabled v dd = 15v, v reg = 3v sleep timer enable, bod disabled v dd = 15v, v reg = 5v sleep timer disabled, bod disabled v dd = 15v, v reg = 3v sleep timer disabled, bod disabled brown-out current ? 0.5 ? av dd = 15v, v reg = 5v, bod enabled brown-out detector threshold b vdd 2.7 1.8 3.1 2.2 4.2 2.8 v v v dd = 15v, v reg = 5v* (7) v dd = 15v, v reg = 3v* (7) regulation voltage v io 2 4 3 5 4.5 6 v v v dd = 15v, v reg = 3v, unloaded outputs, sleep v dd = 15v, v reg = 5v, unloaded outputs, sleep * these parameters are characterized but not tested. note 1: data in the typical ( ? ty p ? ) column is based on characterization results at 25 c. this data is for design guid- ance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 6: the oscillator start-up time can be as much as 8 seconds for xt and lp oscillator selection, if the sleep mode is exited or during initial power-up. 7: see section 7.6.1 for additional information.
? 2000 microchip technology inc. preliminary ds40197b-page 63 pic16hv540 10.2 dc characteristics: pic16hv540-04, 20 (commercial) pic16hv540-04i, 20i (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym. min. typ. (1) max. units conditions input low voltage i/o ports porta mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 i/o ports portb vil vss vss vss vss vss vss ? ? ? ? ? ? 0.10 v reg 0.10 v reg 0.10 v reg 0.10 v reg 0.3 v reg 0.10 v reg v v v v v v pin at hi-impedance rc option only (4) hs, xt, and lp options input high voltage i/o ports porta mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 i/o ports portb vih 0.25 v reg +0.8v 0.85 v reg 0.85 v reg 4.5v 4.5v 0.25 v reg +0.8v ? ? ? ? ? ? v reg v dd v dd v dd v dd v dd v v v v v v for all v reg rc option only (v dd = 15v) (4) hs, xt, and lp options (v dd = 15v) hysteresis of schmitt trigger inputs v hys 0.15 v reg * ?? v input leakage current (3) i/o ports porta i/o ports portb mclr t0cki osc1 i il -1.0 -1.0 -5.0 -3.0 -3.0 0.5 0.5 0.5 0.5 0.5 +1.0 +1.0 +5.0 +3.0 +3.0 +3.0 a a a a a a v ss v pin v io , pin at hi-impedance v ss v pin v dd v pin = v ss +0.25v (2) v pin = v dd (2) v ss v pin v dd v ss v pin v dd , hs, xt, and lp options output low voltage i/o ports porta osc2/clkout i/o ports portb v ol ? ? ? ? ? ? 0.6 0.6 0.6 v v v v dd = 15v, v reg = 5v, i ol = 8.7 ma v dd = 15v, v reg = 3v, i ol = 5.0 ma v dd = 15v, v reg = 5v, i ol = 1.2 ma, (rc option only) v dd = 15v, v reg = 3v, i ol = 1.0 ma, (rc option only) v dd = 15v, v reg = 5v, i ol = 3.0 ma v dd = 10v, v reg = 3v, i ol = 3.0 ma output high voltage i/o ports (3) porta osc2/clkout i/o ports portb v oh v reg -0.7 v reg -0.7 v dd -0.7 ? ? ? ? ? ? v v v v dd = 15v, v io = 3v, i oh = -2.0 ma v dd = 15v, v io = 5v, i oh = -3.0 ma v dd = 15v, v io = 3v, i oh = -0.5 ma (rc option only) v dd = 15v, v io = 5v, i oh = -1.0 ma (rc option only) v dd = 15v, v io = 5v, i oh = -5.4 ma threshold voltage i/o ports portb [7] v lev v dd -1.5 v dd -1.0 v dd -0.5 v v dd = 15v * these parameters are characterized but not tested. note 1: data in the typical ( ? ty p ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels repre- sent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is defined as coming out of the pin. 4: for the rc option, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16hv540 be driven with external clock in rc mode.
pic16hv540 ds40197b-page 64 preliminary ? 2000 microchip technology inc. 10.3 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 10-1: load conditions - pic16hv540 1. tpps2pps 2. tpps t ffrequency ttime lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp options when external clock is used to drive osc1
? 2000 microchip technology inc. preliminary ds40197b-page 65 pic16hv540 10.4 timing diagrams and specifications figure 10-2: external clock timing - pic16hv540 table 10-1: external clock timing requirements - pic16hv540 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) parameter no. sym. characteristic min. typ. (1) max. unit s conditions f osc external clkin frequency (2) dc ? 4.0 mhz rc osc mode dc ? 2.0 mhz hs osc mode dc ? 4.0 mhz xt osc mode dc ? 200 khz lp osc mode oscillator frequency (2) dc ? 4.0 mhz rc osc mode 0.1 ? 2.0 mhz hs osc mode 0.1 ? 4.0 mhz xt osc mode 5 ? 200 khz lp osc mode 1 t osc external clkin period (2) 250 ?? ns rc osc mode 250 ?? ns hs osc mode 250 ?? ns xt osc mode 5.0 ?? s lp osc mode oscillator period (2) 250 ?? ns rc osc mode 250 ? 10,000 ns hs osc mode 250 ? 10,000 ns xt osc mode 50 ? 200 s lp osc mode 2 t cy instruction cycle time (3) ? 4/f osc ?? 3 to s l , to s h clock in (osc1) low or high time 50* ?? ns xt oscillator 20* ?? ns hs oscillator 2.0* ?? s lp oscillator 4 to s r , to s f clock in (osc1) rise or fall time ?? 25* ns xt oscillator ?? 25* ns hs oscillator ?? 50* ns lp oscillator * these parameters are characterized but not tested. note 1: data in the typical ( ? ty p ? ) column is at v reg = 5v, v dd = 9v, 25 c unless otherwise stated. these parame- ters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
pic16hv540 ds40197b-page 66 preliminary ? 2000 microchip technology inc. figure 10-3: clkout and i/o timing - pic16hv540 table 10-2: clkout and i/o timing requirements - pic16hv540 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) parameter no. sym characteristic min typ (1) max units 10 to s h 2 ck l o s c 1 to clkout (2) ? 15 30** ns 11 to s h 2 ck h o s c 1 to clkout (2) ? 15 30** ns 12 tckr clkout rise time (2) ? 5.0 15** ns 13 tckf clkout fall time (2) ? 5.0 15** ns 14 tckl2iov clkout to port out valid (2) ?? 40** ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) ?? 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ?? ns 20 tior port output rise time (3) ? 10 25** ns 21 tiof port output fall time (3) ? 10 25** ns ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical ( ? ty p ? ) column is at v reg = 5v, v dd = 9v, 25 c unless otherwise stated. these parame- ters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 8 x t osc . 3: see figure 10-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 old value new value note: all tests must be done with specified capacitive loads of 50 pf on i/o pins and clkout. 19
? 2000 microchip technology inc. preliminary ds40197b-page 67 pic16hv540 figure 10-4: reset, watchdog timer, and device reset timer timing - pic16hv540 figure 10-5: brown-out detect timing v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 ( note 1 ) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30 35 v reg
pic16hv540 ds40197b-page 68 preliminary ? 2000 microchip technology inc. table 10-3: reset, watchdog timer, and device reset timer - pic16hv540 figure 10-6: timer0 clock timings - pic16hv540 table 10-4: timer0 clock requirements - pic16hv540 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) parameter no. sym characteristic min. typ. (1) max. units conditions 30 tmcl mclr pulse width (low) 2 ?? s v dd = 15v, v reg = 5v 31 twdt watchdog timer time-out period 9.0* 18* 40* ms v dd = 15v, v reg = 5v 32 t drt device reset timer period 9.0* 0.55* 18* 1.1* 30* 2.5* ms v dd = 15v, v reg = 5v, rc mode 34 tio z i/o hi-impedance from mclr low ?? 100* ns ? tpc pin change pulse width 2 ?? s 35 t bod brown-out detect pulse width ? 2 ? s v reg b vdd * these parameters are characterized but not tested. note 1: data in the typical ( ? ty p ? ) column is at v reg = 5v, v dd = 15v, 25 c unless otherwise stated. these param- eters are for design guidance only and are not tested. ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 42 tt0p t0cki period 20 or t cy + 40 * n ?? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical ( ? ty p ? ) column is at 3.8v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2000 microchip technology inc. preliminary ds40197b-page 69 pic16hv540 11.0 dc and ac characteristics - pic16hv540 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside specified operating range (e.g., outside specified v dd range). this is for infor- mation only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? ty p i c a l ? represents the mean of the distribution while ? max ? or ? min ? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 11-1: typical rc oscillator frequency vs. temperature table 11-1: rc oscillator frequencies note 1: this combination of r, c and v dd draws too much current and prohibits oscillator operation. figure 11-2: typical rc oscillator frequency vs. v dd (c ext = 20pf) figure 11-3: typical rc oscillator frequency vs. v dd (c ext = 100pf) c ext r ext average f osc , v io = 5v 25 c, v dd = 6v 25 c, v dd = 15v 20 pf 3.3k 4986.7 khz (1) 5k 4233.3 khz (1) 10k 2656.7 khz 5150.0 khz 24k 1223.3 khz 3286.7 khz 100k 325.7 khz 955.7 khz 390k 79.0 khz 250.7 khz 100 pf 3.3k 1916.7 khz (1) 5k 1593.3 khz (1) 10k 995.7 khz 2086.7 khz 24k 448.3 khz 1210.0 khz 100k 116.0 khz 355.7 khz 390k 28.3 khz 89.7 khz 300 pf 3.3k 744 khz (1) 5k 620.3 khz (1) 10k 382.0 khz 817.3 khz 24k 169.7 khz 483.0 khz 100k 44.1 khz 135.7 khz 390k 10.6 khz 34.4 khz 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 -40 0 25 55 85 te m p ( c ) v dd = 6v v dd = 15v 0.0 1000.0 2000.0 3000.0 4000.0 5000.0 6000.0 3.5 6 9 12 15 v dd (v) freq (khz) r ext = 10k r ext = 24k r ext = 100k r ext = 390k 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3.5 6 9 12 15 v dd (v) freq (khz) r ext = 10k r ext = 24k r ext = 100k r ext = 390k normalized frequency (to 25 c)
pic16hv540 ds40197b-page 70 preliminary ? 2000 microchip technology inc. figure 11-4: typical rc oscillator frequency vs. v dd (c ext = 300pf) figure 11-5: typical i pd vs. v dd , watchdog timer disabled (v io = 5v) figure 11-6: maximum i pd vs. v dd , watchdog timer disabled (v io = 5v) figure 11-7: typical i pd vs. v dd , watchdog timer enabled (v io = 5v) figure 11-8: maximum i pd vs. v dd , watchdog timer enabled (v io = 5v) figure 11-9: typical i pd vs. v dd , watchdog timer disabled (v io = 3v) 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 3.56 91215 v dd (v) freq (khz) r ext = 10k r ext = 24k r ext = 100k r ext = 300k 1.0 1.5 2.0 2.5 3.0 3.5 4.0 691215 v dd (v) i pd (ua) -40 o c 0 o c 85 o c 25 o c 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6 9 12 15 v dd (v) i pd (ua) -40 o c 0 o c 85 o c 25 o c 2.0 3.0 4.0 5.0 6.0 7.0 8.0 6 9 12 15 v dd (v) i pd (ua) -40 o c 0 o c 85 o c 25 o c 3 4 5 6 7 8 9 6 9 12 15 v dd (v) i pd (ua) -40 o c 85 o c 0 o c 25 o c 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 3.5 6 9 12 15 v dd (v) i pd (ua) -40 o c 85 o c 25 o c 0 o c
? 2000 microchip technology inc. preliminary ds40197b-page 71 pic16hv540 figure 11-10: maximum i pd vs. v dd , watchdog timer disabled (v io = 3v) figure 11-11: typical i pd vs. v dd , watchdog timer enabled (v io = 3v) figure 11-12: maximum i pd vs. v dd , watchdog timer enabled (v io = 3v) figure 11-13: maximum i dd vs. frequency, watchdog timer disabled, rc mode (v dd = 15v, v io = 5v, -40 c to +85 c) figure 11-14: maximum i dd vs. frequency, watchdog timer enabled, rc mode (v dd = 15v, v io = 5v) 1 1.5 2 2.5 3 3.5 4 4.5 5 3.5 6 9 12 15 v dd (v) i pd (ua) -40 o c 25 o c 0 o c 85 o c 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 3.5 6 9 12 15 v dd (v) i pd (ua) -40 o c 0 o c 25 o c 85 o c 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 3.5 6 9 12 15 v dd (v) i pd (ua) -40 o c 0 o c 25 o c 85 o c 6.00 5.50 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 400 500 600 700 800 900 1000 3.5 3 2.5 2 1.5 1 0.5 frequency (mhz) i dd ( a) 300 200 100 0 4 400 500 600 700 800 900 1000 3.5 3 2.5 2 1.5 1 0.5 frequency (mhz) i dd ( a) 300 200 100 0 4
pic16hv540 ds40197b-page 72 preliminary ? 2000 microchip technology inc. figure 11-15: i oh vs. v oh on porta, v dd = 15v (v io = 5v) note: current being applied is being applied simultaneously to all 4 porta pins. figure 11-16: i oh vs. v oh on porta, v dd = 5v (v io = 5v) note: current being applied is being applied simultaneously to all 4 porta pins. -12 -10 -8 -6 -4 -2 0 7 6 5 4 3 2 1 0 m a x - 4 0 c t y p i c a l 2 5 c m i n 8 5 c v oh (v) i oh (ma) -12 -10 -8 -6 -4 -2 0 6 5 4 3 2 1 0 m a x - 4 0 c t y p i c a l 2 5 c m i n 8 5 c v oh (v) i oh (ma)
? 2000 microchip technology inc. preliminary ds40197b-page 73 pic16hv540 12.0 packaging information 12.1 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic
pic16hv540 ds40197b-page 74 preliminary ? 2000 microchip technology inc. 12.2 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic
? 2000 microchip technology inc. preliminary ds40197b-page 75 pic16hv540 12.3 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010
pic16hv540 ds40197b-page 76 preliminary ? 2000 microchip technology inc. 12.4 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic
? 2000 microchip technology inc. preliminary ds40197b-page 77 pic16hv540 12.5 package marking information 18-lead pdip example 18-lead soic 20-lead ssop example example legend: mm...m microchip part number information xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 18-lead cerdip windowed example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn xxxxxxxxxxxx xxxxxxxx xxxxxxxx yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn pic16hv540 xxxxxxxxxxxxxxxxx 9923nnn pic16hv540 xxxxxxxxxxxx 9923nnn xxxxxxxxxxxx pic16hv5 xxxxxxxx 9923nnn pic16hv540 xxxxxxxxxxxx 9923nnn
pic16hv540 ds40197b-page 78 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds40197b-page 79 pic16hv540 index a absolute maximum ratings ......................................... 61 alu ............................................................................ 7 applications ................................................................. 3 architectural overview .................................................. 7 assembler mpasm assembler ............................................. 55 b block diagram on-chip reset circuit .......................................... 35 pic16c5x series .................................................. 8 timer0 ............................................................... 25 tmr0/wdt prescaler ......................................... 29 watchdog timer ................................................. 40 brown-out detect ....................................................... 31 c carry bit ...................................................................... 7 clocking scheme ....................................................... 10 code protection ................................................... 31 , 42 configuration bits ....................................................... 31 configuration word .................................................... 31 pic16cr54c ..................................................... 31 d dc and ac characteristics - pic16cr54c ................... 69 dc characteristics ..................................................... 62 development support ................................................. 55 device varieties ........................................................... 5 digit carry bit ............................................................... 7 e electrical characteristics pic16cr54c ..................................................... 61 enhanced watchdog timer (wdt) ............................... 31 errata ......................................................................... 2 external power-on reset circuit .................................. 36 f family of devices pic16c5x ............................................................ 4 features ..................................................................... 1 fsr ......................................................................... 35 fsr register ............................................................. 17 i i/o interfacing ............................................................ 19 i/o ports ................................................................... 19 i/o programming considerations ................................. 22 indf ........................................................................ 35 indf register ............................................................ 17 indirect data addressing ............................................. 17 instruction cycle ........................................................ 10 instruction flow/pipelining ........................................... 10 instruction set summary ............................................. 43 k keeloq ? evaluation and programming tools ............... 58 l load conditions ......................................................... 64 loading of pc ............................................................ 16 m mclr ................................................................................. 35 memory map ............................................................. 11 pic16c54s/cr54s/c55s ..................................... 11 memory organization ................................................. 11 data memory ..................................................... 11 program memory ................................................ 11 mplab integrated development environment software .. 55 o one-time-programmable (otp) devices ........................ 5 option register ....................................................... 14 osc selection ............................................................ 31 oscillator configurations ............................................. 32 oscillator types hs .................................................................... 32 lp ..................................................................... 32 rc .................................................................... 32 xt ..................................................................... 32 p package marking information ...................................... 77 packaging information ................................................ 73 pc ......................................................................16 , 35 picdem-1 low-cost picmicro demo board ................. 57 picdem-2 low-cost pic16cxx demo board ............... 57 picdem-3 low-cost pic16cxxx demo board ............. 57 picstart ? plus entry level development system ...... 57 pin diagrams ................................................................ 1 por device reset timer (drt) .............................31 , 38 pd .......................................................................34 , 41 power-on reset (por) .......................... 31 , 35 , 36 to .......................................................................34 , 41 porta ...............................................................19 , 35 portb ...............................................................19 , 35 power-down mode ..................................................... 41 prescaler ................................................................... 28 pro mate ? ii universal programmer ......................... 57 program counter ....................................................... 16 q q cycles .................................................................... 10 quick-turnaround-production (qtp) devices .................. 5 r rc oscillator ............................................................. 33 read-modify-write ..................................................... 22 register file map ....................................................... 11 registers special function ................................................. 11 reset ..................................................................31 , 34 s seeval ? evaluation and programming system ........... 58 serialized quick-turnaround-production (sqtp) devices .5 sleep ................................................................31 , 41 software simulator (mplab-sim) ................................ 56 special features of the cpu ....................................... 31 special function registers .......................................... 11 stack ........................................................................ 16 status ................................................................... 35 status register ...................................................7 , 13 t timer0 switching prescaler assignment ........................... 28 timer0 (tmr0) module ........................................ 25 tmr0 with external clock .................................... 27 timing diagrams and specifications ............................. 65 timing parameter symbology and load conditions ........ 64 tris registers .......................................................... 19 u uv erasable devices .................................................... 5 w w ............................................................................. 35 wake-up from sleep ................................................. 41 wake-up from sleep on pin change ........................... 31 watchdog timer (wdt) .............................................. 39
pic16hv540 ds40197b-page 80 preliminary ? 2000 microchip technology inc. period ................................................................ 39 programming considerations ............................... 39 www, on-line support ................................................ 2 z zero bit ....................................................................... 7
? 2000 microchip technology inc. preliminary ds40197b-page 81 pic16hv540 on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmi- cro, picstart, picmaster, pro mate and mplab are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the prop- erty of their respective companies. 991103
pic16hv540 ds40197b-page 82 preliminary ? 2000 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40197b pic16hv540 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products?
? 2000 microchip technology inc. preliminary ds40197b-page 83 pic16hv540 pic16hv540 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support pattern: qtp,sqtp, code or special requirements package: jw = windowed cerdip so = soic p=pdip ss = ssop temperature -= ? 0 c to +70 c range: i= ? 40 c to +85 c frequency 04 = 200 khz (pichv540-04) range 04 = 4 mhz 20 = 20 mhz device: pic16hv540 :v dd range 3.5v to 15v pic16hv540t :v dd range 3.5v to 15v (tape/reel) pic16hv540 -xx x /xx xxx data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277. 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 03/01/02 w orldwide s ales and s ervice

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